Engineering portfolio

DanielJoseph.

Exploring how hardware and software come together, one engineering project at a time.

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Illustrative processor datapath connecting instruction memory, control, registers, and an arithmetic logic unitREGISTERSALUMEMORYCONTROL

01 / COMPUTER ARCHITECTURE — DATAPATH STUDY

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01 / PROJECTS
Computer architecture

RV32I processor core

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A single-cycle RV32I core in SystemVerilog, with cocotb tests and an iCEBreaker FPGA demo.

Explore the source code, testing setup, and project documentation on GitHub.

RISC-VSystemVerilogcocotbFPGA
02 / ABOUT

Learning by building.

I'm Daniel Joseph. This portfolio brings together my engineering projects and the work behind them.

My featured project explores processor design, connecting digital hardware with the software used to test it.

03 / CONNECT

Follow what I'm building.

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